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TDA8023
Low power IC card interface
Rev. 01 -- 16 July 2007 Product data sheet
1. General description
The TDA8023 is a complete cost-efficient, low-power analog interface for synchronous or asynchronous smart cards. It can be placed between the card and the microcontroller with very few external components to perform all supply, protection and control functions.
2. Features
I I I I I I I I I I2C-bus controlled IC card interface in TSSOP28 Supply voltage from 2.7 V to 6.5 V Independant supply voltage VDD(INTF) for interface signals with the microcontroller Shutdown input for very low power consumption when the part is not used Power reduction modes when the card is active DC-to-DC converter for VCC generation (capacitive doubler, tripler, or inductive, or follower automatically selected according to supply voltage and card voltage) 1 specific protected half duplex bidirectional buffered I/O line, with current limitation at 15 mA, maximum frequency 1 MHz 2 auxiliary card I/O lines controlled by I2C-bus (C4 and C8) VCC regulation: 5 V, 3 V or 1.8 V 8 %, ICC < 55 mA, current spikes of 40 nAs up to 20 MHz, with controlled rise and fall times, filtered overload detection approximately 80 mA, current limitation about 120 mA Thermal and short-circuit protections on all card contacts Automatic activation and deactivation sequences: initiated by software or by hardware in the event of a short-circuit, card take-off, overheating, VDD or VDD(DCDC) drop-out Enhanced ElectroStatic Discharge (ESD) protection on card side (> 6 kV) 20 MHz clock input Clock generation for the card up to 10 MHz (CLKIN divided by 1, 2, 4 or 5) with synchronous frequency changes; stop HIGH or LOW or free running 1 MHz in cards Low-power mode; current limitation on pin CLK (C3) RST signal (C2) with current limitation at 20 mA, controlled by an embedded programmable CLK pulse counter on asynchronous cards or by a register on synchronous cards ISO 7816-3, GSM 11.11 and EMV 2000 (payment systems) compatibility Supply voltage supervisor for spike killing during power-on and emergency deactivation at power-off: threshold internally fixed or set via an external resistor bridge; pulse width internally fixed or set via an external capacitor Card presence input with 10 ms built-in debouncing system One interrupt signal INT
I I I I I
I
I I
I I
NXP Semiconductors
TDA8023
Low power IC card interface
3. Applications
I I I I Banking terminals Internet terminals Set-top boxes Portable IC card readers
4. Quick reference data
Table 1. Quick reference data VDD = 3.3 V; VDD(INTF) = 1.5 V; fCLKIN = 10 MHz; GND = 0 V; Tamb = 25 C; unless otherwise specified. Symbol Supply VDD VDD(DCDC) VDD(INTF) IDD supply voltage DC-to-DC converter supply voltage supply current on pin VDD on pin VDDP 2.7 2.7 1.5
[1] [1] [1]
Parameter
Conditions
Min
Typ -
Max 6.5 6.5 6.5 10 200 15 200 15 150 2
Unit V V V A A mA mA mA mA mA
interface supply voltage on pin VDDI Shutdown mode Inactive mode; CLKIN LOW or HIGH Active mode; VCC = 5 V; fCLK = 5 MHz capacitive; ICC = 5 mA capacitive; ICC = 55 mA inductive; ICC = 5 mA inductive; ICC = 55 mA Power-down mode; VCC = 5 V; ICC = 100 A; CLK stopped; CLKIN HIGH or LOW; capacitive or inductive
[1]
-
Supply voltage for the card: pin VCC[2] VCC supply voltage Active mode; 2.7 V < VDD < 6.5 V 5 V card; ICC < 60 mA; VCC = 5 V 3 V card; ICC < 55 mA; VCC = 3 V 1.8 V card; ICC < 30 mA; VCC = 1.8 V Active mode; AC current pulses with I < 200 mA, t < 400 ns and f < 20 MHz 5 V card; current pulses of 40 nAs 3 V card; current pulses of 24 nAs 1.8 V card; current pulses of 15 nAs Vripple(p-p) ICC peak-to-peak ripple voltage supply current on VCC; 20 kHz to 200 MHz VDD > 2.7 V 5 V card; VCC = 0 V to 5 V 3 V card; VCC = 0 V to 3 V 1.8 V card; VCC = 0 V to 1.8 V -55 -55 -35 mA mA mA
[3] [3]
4.75 2.80 1.65
5 3 1.8
5.25 3.15 1.95
V V V
4.65 2.76 1.62 -
-
5.35 3.24 1.98 350
V V V mV
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Product data sheet
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TDA8023
Low power IC card interface
Table 1. Quick reference data ...continued VDD = 3.3 V; VDD(INTF) = 1.5 V; fCLKIN = 10 MHz; GND = 0 V; Tamb = 25 C; unless otherwise specified. Symbol General tdeact Ptot Tamb
[1] [2] [3]
Parameter deactivation time total power dissipation ambient temperature
Conditions total sequence Tamb = -25 C to +85 C
Min 60 -40
Typ 80 -
Max 100 500 +85
Unit s mW C
Sum of currents on pins VDD and VDDI. Two ceramic multilayer capacitors of minimum 100 nF with low Equivalent Series Resistance (ESR) should be used in order to meet these specifications. Output voltage towards the card, including ripple.
5. Ordering information
Table 2. Ordering information Package Name TDA8023TT TSSOP28 Description plastic thin shrink small outline package; 28 leads; body width 4.4 mm Version SOT361-1 Type number
6. Block diagram
optional external resistor bridge
R2
100 nF
1 F
100 nF
100 nF
VDD 22 PORADJ 20
VDDP SBP 26 27
SBM 25
SAM 23
SAP 28 24 GNDP
R1
CDEL 21
CCDEL
SUPPLY SUPERVISOR
DC-TO-DC CONVERTER 1 VUP
100 nF
GND 10
TDA8023
VDDI SDWN SDA SCL CLKIN I/OUC INT SPRES SAD0 4 3 5 6 9 11 2 8 7 I2C-BUS INTERFACE SEQUENCER CLOCK COUNTER CARD DRIVERS 18 16 14 13 12 19 15 17 VCC 100 nF
RST CLK I/O C4 C8 PRES GNDC
001aag336
Fig 1. Block diagram with capacitive DC-to-DC converter
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TDA8023
Low power IC card interface
optional external resistor bridge
R2
100 nF 10 F
LX 6.8 H
VDD 22 PORADJ 20
VDDP SBP 27 26
SBM 25
SAM 23
SAP 28 24 GNDP
R1
CDEL 21
CCDEL
SUPPLY SUPERVISOR
DC-TO-DC CONVERTER
1 VUP
100 nF 4.7 F
GND 10
TDA8023
VDDI SDWN SDA SCL CLKIN I/OUC INT SPRES SAD0 4 3 5 6 9 11 2 8 7 I2C-BUS INTERFACE SEQUENCER CLOCK COUNTER CARD DRIVERS 18 16 14 13 12 19 15 17 VCC 100 nF
RST CLK I/O C4 C8 PRES GNDC
001aag337
Fig 2. Block diagram with inductive DC-to-DC converter
7. Pinning information
7.1 Pinning
VUP INT SDWN VDDI SDA SCL SAD0 SPRES CLKIN
1 2 3 4 5 6 7 8 9
28 SAP 27 SBP 26 VDDP 25 SBM 24 GNDP 23 SAM 22 VDD 21 CDEL 20 PORADJ 19 PRES 18 RST 17 VCC 16 CLK 15 GNDC
001aag338
TDA8023TT
GND 10 I/OUC 11 C8 12 C4 13 I/O 14
Fig 3. Pin configuration TDA8023TT
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TDA8023
Low power IC card interface
7.2 Pin description
Table 3. Symbol VUP INT Pin description Pin 1 2 Type[1] O O Description output of the DC-to-DC converter Negative-channel Metal Oxide Semiconductor (NMOS) interrupt to the host (active LOW and open-drain) (see fault detection in Section 8.7 "Protection") shutdown and reset input interface positive supply voltage serial data line to/from the I2C-bus master (open-drain) serial clock line from the I2C-bus master I2C-bus address selection select PRES mode[2] external clock input ground connection data in/out from/to microcontroller auxiliary input/output to/from the card (contact C8) auxiliary input/output to/from the card (contact C4) data input/output to/from (contact C7 of) the card ground connection for the card (contact C5) clock output to (contact C3 of) the card supply voltage for the card (contact C1) reset output to (contact C2 of) the card card presence input with a 10 ms built-in debouncing system[2] input for changing the power-on reset threshold with an external resistor bridge. In case no external resistor bridge is used, it is mandatory to connect this pin to GND to avoid possible perturbations. CDEL VDD SAM GNDP SBM VDDP SBP SAP
[1] [2] [3] [4]
SDWN VDDI SDA SCL SAD0 SPRES CLKIN GND I/OUC C8 C4 I/O GNDC CLK VCC RST PRES PORADJ
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
I S I/O I I I I S I/O[3] I/O[4] I/O[4] I/O[4] S O S O I I
21 22 23 24 25 26 27 28
C S C S C S C C
delay capacitor connection for the voltage supervisor (1 ms per 2 nF) power supply connection for the DC-to-DC converter ground connection for the DC-to-DC converter connection for the DC-to-DC converter positive supply for the DC-to-DC converter connection for the DC-to-DC converter connection for the DC-to-DC converter
I = input, O = output, S = supply, C = configuration. PRES is active-HIGH when SPRES = LOW and PRES is active-LOW when SPRES = HIGH. With integrated pull-up to VDD(INTF). With integrated pull-up to VCC.
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TDA8023
Low power IC card interface
8. Functional description
Remark: Throughout this document, it is assumed that the reader is familiar with ISO 7816 and EMV 2000 terminology.
8.1 Power supplies
The supply pins for the TDA8023 are VDD and GND. VDD should be in the range from 2.7 V to 6.5 V. The supply voltages VDD, VDD(INTF) and VDD(DCDC) may be applied to the TDA8023 in any time sequence. All interface signals with the system controller are referenced to a separate supply voltage VDD(INTF) on pin VDDI, that may be lower or higher than VDD. For generating a supply voltage VCC of 5 V 5 % or 3 V 5 % used by the card, an integrated DC-to-DC converter is incorporated. This DC-to-DC converter should be separately supplied by VDD(DCDC) on pin VDDP and GNDP (from 2.7 V to 6.5 V). The I2C-bus signals SDA and SCL may be externally referenced to a voltage higher than VDD.
8.2 Voltage supervisor
8.2.1 Without external divider on pin PORADJ
The voltage supervisor surveys the VDD supply voltage. It is used as Power-On Reset (POR) and as supply dropout detection during a card session. Supply dropout detection ensures that a proper deactivation sequence is followed before the voltage is too low. A reset pulse of duration tW (see Figure 4) is used internally for maintaining the TDA8023 in the Inactive mode during powering up or powering down of VDD. As long as VDD is less than Vth(POR)H the TDA8023 will remain inactive whatever the levels on the command lines are. This also lasts for the duration of tW after VDD has reached a level higher than Vth(POR)H. When VDD falls below Vth(POR)L an automatic deactivation sequence of the contacts is performed. In this case (no external resistor bridge) it is mandatory to connect pin PORADJ to GND.
power on VDD status read
shutdown mode
power off Vth(POR)H Vth(POR)L status read Vhys(POR)
INT tW tW
SDWN
bus unresponsive
bus unresponsive
bus unresponsive
001aag339
Fig 4. Voltage supervisor and Shutdown mode
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TDA8023
Low power IC card interface
8.2.2 With external divider on pin PORADJ
If an external resistor bridge is connected to pin PORADJ (R1 to GND and R2 to VDD as shown in Figure 1 and Figure 2), then the internal threshold voltages and the internal hysteresis voltage are overridden by externally determined ones. The voltage on pin PORADJ is: R1 V PORADJ = ------------------- x V DD = k x V DD R1 + R2 where R1 k = ------------------R1 + R2 The thresholds that are applied by the TDA8023 to this voltage VPORADJ are: V hys V th ( H ) ( PORADJ ) = V bg ( int ) + ---------- (rising) 2 V hys V th ( L ) ( PORADJ ) = V bg ( int ) - ---------- (falling) 2 where Vbg(int) = 1.25 V (typ) Vhys = 60 mV (typ) The thresholds and hysteresis on VDD can then be calculated from: V V + hys V th ( H ) ( PORADJ ) bg ( int ) ---------- 2 = ------------------------------------- = ----------------------------------------- (rising) k k V V - hys V th ( L ) ( PORADJ ) bg ( int ) ---------- 2 = ------------------------------------ = ---------------------------------------- (falling) k k
V th ( POR )H
V th ( POR )L
V hys V hys ( POR ) = ---------k The minimum threshold voltage Vth(POR)L should be chosen higher than 2 V. Input PORADJ is biased internally with a pull-down current source of 4 A which is cut when the voltage on this pin exceeds 1 V. This ensures that after detection of the external bridge during power-on, the input current on this pin does not cause inaccuracy of the bridge voltage.
8.2.3 External capacitor on pin CDEL
The width of the POR pulse (tW) is externally set by the value of the CDEL capacitor: the typical value is 1 ms per 2 nF. Usually CCDEL = 22 nF, therefore tW = 10 ms (typ).
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TDA8023
Low power IC card interface
8.2.4 Shutdown mode
When pin SDWN = HIGH, the TDA8023 is in Shutdown mode; the consumption in this mode is less than 10 A. The I2C-bus is unresponsive. If the card is extracted or inserted when the TDA8023 is in Power-down mode, pin INT becomes LOW and stays LOW as long as pin SDWN = HIGH. When pin SDWN is pulled LOW, the TDA8023 leaves Shutdown mode and executes a complete power-on reset sequence.
8.3 I2C-bus
A 400 kHz I2C-bus slave interface is used for configuring the TDA8023 and reading the status.
8.3.1 I2C-bus protocol
The I2C-bus is for 2-way 2-line communication between ICs or modules. The serial bus consists of two bidirectional lines: one for data signals (SDA) and one for clock signals (SCL). Both the SDA and SCL lines must be connected to a positive supply voltage via a pull-up resistor. The following protocol has been defined:
* Data transfer may be initiated only when the bus is not busy * During data transfer, the data line must remain stable whenever the clock line is
HIGH; changes in the data line while the clock line is HIGH will be interpreted as control signals
8.3.2 Bus conditions
The following bus conditions have been defined. Bus not busy -- Both data and clock lines remain HIGH. Start data transfer -- A change in the state of the data line from HIGH to LOW, while the clock is HIGH, defines the START condition. Stop data transfer -- A change in the state of the data line from LOW to HIGH, while the clock is HIGH, defines the STOP condition. Data valid -- The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. There is one clock pulse per bit of data.
8.3.3 Data transfer
Each data transfer is initiated with a START condition and terminated with a STOP condition (see Figure 7). See Table 15 for timing information. Data transfer is unlimited in the Read mode. The information is transmitted in bytes and each receiver acknowledges with a 9th bit.
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Product data sheet
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TDA8023
Low power IC card interface
Within the I2C-bus specifications, a Standard mode (100 kHz clock rate) and a Fast-speed mode (400 kHz clock rate) are defined. The TDA8023 operates in both Fast-speed and Standard modes. By definition, a device that sends a signal is called a transmitter and a device that receives the signal is called a receiver. The device that controls the signal is called the master. The devices that are controlled by the master are called slaves. Each byte is followed by one acknowledge bit. This acknowledge bit is a HIGH level, put on the bus by the transmitter. The master generates an extra acknowledge-related clock pulse. The slave receiver that is addressed is obliged to generate an acknowledge after the reception of each byte. The master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge-related clock pulse. Set-up and hold times must be taken into account. A master receiver must signal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master generation of the STOP condition.
8.3.4 Device addressing
Each TDA8023 has 2 different addresses, one for each of its two registers. Two TDA8023s may be used in parallel due to the address selection pin SAD0. Pin SAD0 is externally hardwired to pin VDD or pin GND. The voltage on pin SAD0 sets address bit b2: HIGH sets bit b2 to logic 1, LOW resets b2 to logic 0. Address bit b1 selects Register 0 or Register 1. Address bit b0 defines Read or Write operation: 1 means Read, 0 means Write. The addresses for the TDA8023 are shown in Table 4 and Table 5.
Table 4. b7 0 Table 5. Pin SAD0 L H Device addressing b6 1 b5 0 b4 0 b3 0 b2 SAD0 b1 0/1 b0 R/W
I2C-bus addresses for write mode Register 0 40h 44h Register 1 42h 46h
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TDA8023
Low power IC card interface
8.3.5 Registers
Table 6. Bit Table of registers Register 0 Read mode Status 7 6 5 4 3 2 1 0 ACTIVE EARLY MUTE PROT SUPL CLKSW PRESL PRES Write mode Command VCC1V8 I/OEN REG1 REG0 PDWN 5V/3VN WARM START Table 7. Bit 7 6 5 4 3 2 1 0 Register 1 Read/Write mode REG1 = 0 REG0 = 0 TEST RSTIN C8 C4 CLKPD2 CLKPD1 CLKDIV2 CLKDIV1 REG0 = 1 D7 D6 D5 D4 D3 D2 D1 D0 REG1 = 1 REG0 = 0 C15 C14 C13 C12 C11 C10 C9 C8 REG0 = 1 C7 C6 C5 C4 C3 C2 C1 C0
Status - Register 0 in Read mode bit description Symbol ACTIVE EARLY MUTE PROT SUPL CLKSW PRESL PRES Description set if the card is active; reset if the card is inactive set during Answer To Reset (ATR) when the selected card has answered too early set during ATR when the card has not answered during the ISO 7816 time slots set when an overload or an overheating has occurred during a session; reset when the status has been read set when the voltage supervisor has signalled a fault; reset when the status has been read set when the TDA8023 is in Power-down mode and the clock has changed set when the card has been inserted or extracted; reset when the status has been read set when the card is present; reset when the card is not present
When at least one of the bits PRESL, PROT, MUTE and EARLY is set, pin INT goes LOW until the status byte has been read. After power-on, bit SUPL is set until the status byte has been read, and pin INT = LOW until the voltage supervisor becomes inactive.
Table 8. Bit 7 Command - Register 0 in Write mode bit description Symbol VCC1V8 Description 1: VCC = 1.8 V 0: VCC is defined by bit 5V/3VN this bit can not change if bit START is logic 1 6 5 and 4 I/OEN REG[1:0] 1: signal on pin I/OUC is transferred to pin I/O 0: pin I/OUC and pin I/O are high-impedance selection of subaddress in Register 1 (see Table 9, 10, 11 and 12)
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TDA8023
Low power IC card interface
Command - Register 0 in Write mode bit description ...continued Symbol PDWN Description 1: applies on pin CLK the frequency that is defined by bits CLKPD[2:1] and reduces power consumption (in Synchronous mode); this bit can not change if bit START is logic 1 1: VCC = 5 V 0: VCC = 3 V this bit can not change if bit START is logic 1
Table 8. Bit 3
2
5V/3VN
1
WARM
1: initiates a warm reset procedure this bit will be automatically reset by hardware when bit MUTE is set to logic 1
0
START
1: initiates an activation sequence and a cold reset procedure (only if bit SUPL = 0 and the bit PRES = 1) 0: initiates a deactivation sequence
Table 9. Bit 7 6
R1_00 - Register 1 subaddress 00 in Read/Write mode bit description Symbol TEST RSTIN[1] Description 1: the circuit is in Test mode 0: the circuit is in Operational mode defines the voltage on pin RST: 1: VCC 0: 0 V
5
C8
defines the voltage on pin C8: 1: VCC 0: 0 V
4
C4
defines the voltage on pin C4: 1: VCC 0: 0 V
3 and 2
CLKPD[2:1]
clock pulse definition: 00: CLK stop LOW 01: CLK stop HIGH 10: frequency on pin CLK: fCLK = fosc(int) / 2 11: no change in Synchronous mode bit CLKPD2 is always logic 0 by hardware and bit CLKPD1 controls the voltage on pin CLK: 1: VCC 0: 0 V
1 and 0
CLKDIV[2:1]
clock divider: 00: fCLK = fCLKIN 01: fCLK = fCLKIN / 2 10: fCLK = fCLKIN / 4 11: fCLK = fCLKIN / 5 in Synchronous mode, bits CLKDIV[2:1] are always 00 by hardware
[1]
Synchronous or asynchronous cards management are defined when bit START is set: the TDA8023 will be in asynchronous cards management when bit RSTIN = 1 when bit START is set to logic 1.
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Low power IC card interface
R1_01 - Register 1 subaddress 01 in Read/Write mode bit description Symbol D[7:0] Description 8-bit programmable CLK period count register; range: 0 to 255; initial value: 170
Table 10. Bit 7 to 0
Table 11. Bit 7 to 0
R1_10 - Register 1 subaddress 10 in Read/Write mode bit description Symbol C[15:8] Description 8-bit programmable CLK period count register; range in combination with C[7:0]: 0 to 65535; initial value: 164
Table 12. Bit 7 to 0
R1_11 - Register 1 subaddress 11 in Read/Write mode bit description Symbol C[7:0] Description 8-bit programmable CLK period count register; range in combination with C[15:8]: 0 to 65535; initial value: 116
If bit RSTIN = 0 when bit START is set to logic 1, then pin RST is controlled by bit RSTIN. Else, pin RST = LOW during a number of CLK periods, defined by the 16-bit CLK count register C[15:0], and goes HIGH afterwards. There are two synchronous card management types:
* If bit PDWN = 0 when bit START is set to logic 1, then the output CLK is controlled by
input CLKIN (without division)
* If bit PDWN = 1 when bit START is set to logic 1, then the output CLK is controlled by
bit CLKPD1
8.4 DC-to-DC converter
For generating a supply voltage VCC of 5 V 5 % or 3 V 5 % to the card, an integrated voltage converter is incorporated. This DC-to-DC converter should be separately supplied by VDD(DCDC) on pin VDDP and GNDP (from 2.7 V to 6.5 V). The DC-to-DC conversion is either capacitive or inductive, according to the external components (automatic detection).
8.4.1 Capacitive configuration
The external components are three 100 nF capacitors (low-ESR), see Figure 1. The DC-to-DC converter is either tripler, doubler or follower according to the respective values of VCC and VDD(DCDC). An hysteresis of 100 mV is present on both thresholds:
* Follower:
- If VCC = 5 V and VDD(DCDC) > 5.8 V - If VCC = 3 V and VDD(DCDC) > 4 V - If VCC = 1.8 V
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Low power IC card interface
* Doubler:
- If VCC = 5 V and VDD(DCDC) = 4 V to 5.8 V - If VCC = 3 V and VDD(DCDC) < 4 V
* Tripler:
- If VCC = 5 V and VDD(DCDC) < 4 V
8.4.2 Inductive configuration
The external components are a diode, a coil of 6.8 H and a capacitor of 4.7 F (see Figure 2). In this configuration the DC-to-DC converter acts as follows.
* If VCC = 5 V then VVUP is regulated at 5.5 V * If VCC = 3 V then VVUP is regulated at 4 V * If VCC = 1.8 V then the DC-to-DC converter acts as a follower 8.5 VCC buffer
In all modes (follower, doubler, tripler), the DC-to-DC converter is able to deliver 60 mA over the whole VDD range (2.7 V to 6.5 V) or 90 mA if VDD > 3 V. The current on the VCC buffer has an internal limitation of around 90 mA. When this limit is reached, an automatic deactivation sequence is performed. The VCC voltage should be decoupled with a low-ESR capacitor between 100 nF and 168 nF. If the card socket is not very close to the TDA8023, one capacitor should be placed near the TDA8023, and a second one near the card contacts.
8.6 Sequencer and clock counter
The sequencer takes care of ensuring activation and deactivation sequences according to ISO 7816 and EMV 2000, even in case of emergency (card removal during transaction, supply dropout or hardware problem). The sequencer is clocked with an internal oscillator. The activation of a card is initiated by setting bit START in the Command register, which is only possible if the card is present and if the voltage supervisor is not active. The activation sequence is described in Section 8.6.1. The deactivation is initiated either by the system controller or automatically in case of a hardware problem or a supply dropout. The deactivation sequence is described in Section 8.6.2. Outside a session, card contacts are forced low-impedance with respect to pin GNDC.
8.6.1 Activation sequence
When the card is inactive, pins VCC, CLK, RST and I/O are LOW, which is low-impedance with respect to pin GNDC. The DC-to-DC converter is stopped.
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Low power IC card interface
When everything is satisfactorily present (voltage supply, card present, no hardware problems) the system controller may initiate an activation sequence of a present card: 1. The internal oscillator changes to its high frequency (t0, see Figure 5). 2. The DC-to-DC converter is started (t1). 3. VCC starts rising from 0 V to 5 V, 3 V or 1.8 V with a controlled rise time (t2). 4. The voltage on pin I/O rises to VCC, due to integrated 14 k pull-ups to VCC (t3). 5. CLK is sent to the card and pin RST is enabled (t4 = tact). During the activation sequence, the answer from the card (ATR) is monitored and the steps are the following: 1. If a start bit is detected on pin I/O during the first 200 CLK pulses, then it is simply ignored, and the CLK count goes on. 2. If a start bit is detected whilst pin RST = LOW (between 200 and 42100 CLK pulses or the value written in C[15:0]), then the bits EARLY and MUTE are set in the Status register. Pin RST will remain LOW. It is up to the software to decide whether to accept the card or not. 3. If no start bit has been detected within 42100 CLK pulses, then pin RST is toggled to HIGH (t5). 4. If, again, a start bit is detected within 370 CLK pulses (200 + 170 or the value defined in D[7:0]), bit EARLY in the Status register is set. 5. If the card does not answer within 42100 new CLK pulses, then bit MUTE in the Status register is set. 6. If the card answers within the correct time window, then the CLK count is stopped and the system controller can send commands to the card. f osc ( int ) The sequencer is clocked by ------------------- which leads to a time interval T = 25 s (typical). 64 T 7T 3T Thus t 1 = 0 s to ----- , t 2 = t 1 + ------ , t 3 = t 1 + ------ and t 4 = t 1 + 4T . 64 2 2
START
VUP
VCC I/O
CLK
RST t0 t1 t2 t3 t4 t5 ATR
tact
001aag340
Fig 5. Activation sequence
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TDA8023
Low power IC card interface
8.6.2 Deactivation sequence
When the session is completed, the microcontroller resets bit START to logic 0 (t10, see Figure 6). The circuit then executes an automatic deactivation sequence: 1. Card reset: pin RST falls to LOW (t11). 2. CLK is stopped (t12). 3. Pin I/O falls to 0 V (t13). 4. Pin VCC falls to 0 V with a controlled slew rate (t14). 5. The DC-to-DC converter is stopped and pins CLK, RST, VCC and I/O become low-impedance with relation to GNDC (t15). 6. The internal oscillator changes to its low frequency (t15). T T 3T 7T t 11 = t 10 + ----- , t 12 = t 11 + --- , t 13 = t 11 + T , t 14 = t 11 + ------ and t 15 = t 11 + ------ . 2 64 2 2 The deactivation time tdeact is the time that VCC needs for going down to less than 0.4 V, counted from the moment bit START is reset.
START
RST CLK
I/O
VCC
VUP t10 t11 t12 t13 tdeact t14 t15
001aag619
Fig 6. Deactivation sequence
8.7 Protection
All card contacts are protected against any short with any other card contact. The currents on various pins are limited:
* * * *
on pin CLK: limited to 70 mA on pin I/O: limited to 10 mA (typical value) on pin RST: limited (only when this pin is LOW) to 20 mA on pin VCC: limited to 90 mA
If any of these currents exceeds its limit, an emergency deactivation sequence is performed: pin INT is pulled LOW and bit PROT in the Status register is set.
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Low power IC card interface
In case of overcurrent on pin VCC, removal of the card during a session, overheating, supply dropout, DC-to-DC out of limits, or overcurrent on pin RST, the TDA8023 performs an automatic emergency deactivation sequence on the card, resets bit START and pulls pin INT LOW.
9. Limiting values
Table 13. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDD VDD(DCDC) VDD(INTF) VIH Parameter supply voltage DC-to-DC converter supply voltage interface supply voltage Conditions on pin VDD on pin VDDP on pin VDDI on pins SDA, SCL on all other pins Ptot Tstg Tj Vesd total power dissipation storage temperature junction temperature electrostatic discharge voltage Human Body Model (HBM) on card pins I/O, VCC, CLK, GNDC, PRES, RST on all other pins Machine Model (MM) all pins, excluding card pins
[1]
[1]
Min -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -55 -6 -2 -200
Max +6.5 +6.5 +6.5 +7.5 +6.5 500 +150 150 +6 +2 +200
Unit V V V V V mW C C kV kV V
HIGH-level input voltage on pins SAP, SAM, SBP, SBM, VUP
VDD + 0.5 V
Tamb = -25 C to +85 C
Every pin withstands the ESD test according to MIL-STD-883C class 3 for card contacts, class 2 for the remaining. Method 3015 (HBM; 1500 ; 100 pF) defines 3 pulses positive and 3 pulses negative on each pin referenced to ground.
10. Thermal characteristics
Table 14. Symbol Rth(j-a) Thermal characteristics Parameter thermal resistance from junction to ambient Conditions in free air Typ 100 Unit K/W
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11. Characteristics
Table 15. Supply VDD = 3.3 V; VDD(INTF) = 1.5 V; fCLKIN = 10 MHz; GND = 0 V; Tamb = 25 C; unless otherwise specified. Symbol VDD VDD(DCDC) VDD(INTF) IDD Parameter supply voltage DC-to-DC converter supply voltage interface supply voltage supply current Conditions on pin VDD on pin VDDP on pin VDDI Shutdown mode Inactive mode; CLKIN LOW or HIGH Active mode; VCC = 5 V; fCLK = 5 MHz capacitive; ICC = 5 mA capacitive; ICC = 55 mA inductive; ICC = 5 mA inductive; ICC = 55 mA Power-down mode; VCC = 5 V; ICC = 100 A; CLK stopped; CLKIN HIGH or LOW; capacitive or inductive IDD(INTF) Vth(POR)L Vhys(POR) interface supply current on pin VDDI LOW-level power-on reset decreasing voltage on pin VDD; see Figure 4 threshold voltage power-on reset hysteresis on pin VDD; see Figure 4 voltage
[1] [1] [1] [1]
Min 2.7 2.7 1.5 -
Typ -
Max 6.5 6.5 6.5 10 200 15 200 15 150 2
Unit V V V A A mA mA mA mA mA
2.30 50
-
120 2.60 150
A V mV
[1]
Sum of currents on pins VDD and VDDI.
Table 16. Supply supervisor VDD = 3.3 V; VDD(INTF) = 1.5 V; fCLKIN = 10 MHz; GND = 0 V; Tamb = 25 C; unless otherwise specified. Symbol Pin PORADJ Vth(H)(PORADJ) Vth(L)(PORADJ) Vhys Vth/T IL Pin CDEL VCDEL ICDEL tW
TDA8023_1
Parameter HIGH-level threshold voltage on pin PORADJ LOW-level threshold voltage on pin PORADJ hysteresis voltage threshold voltage variation with temperature leakage current
Conditions rising voltage; see Section 8.2.2 falling voltage; see Section 8.2.2 Vth(H)(PORADJ) - Vth(L)(PORADJ); see Section 8.2.2 on Vth(H)(PORADJ) and Vth(L)(PORADJ) VPORADJ < 0.6 V VPORADJ > 0.8 V
Min 1.25 1.19 30 0 -1 -
Typ 1.28 1.22 60 4 -2 -5 10
Max 1.31 1.25 90 0.25 10 +1 VDD + 0.3 0 -
Unit V V mV mV/C A A V A mA ms
voltage on pin CDEL current on pin CDEL pulse width pin grounded (charge) VCDEL = VDD (discharge) internal alarm pulse; CCDEL = 22 nF
Rev. 01 -- 16 July 2007
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Table 17. DC-to-DC converter VDD = 3.3 V; VDD(INTF) = 1.5 V; fCLKIN = 10 MHz; GND = 0 V; Tamb = 25 C; unless otherwise specified. Symbol fosc(int) VVUP Parameter internal oscillator frequency voltage on pin VUP 5 V card 3 V card 1.8 V card Vdet detection voltage on pin VDDP 5 V card; Follower mode 3 V card; Follower mode 5 V card; Tripler mode 5.5 3.8 5.8 4 3.5 6 4.2 V V V Conditions Min 2 5.3 3.5 Typ 2.5 5.5 4 VDD(DCDC) Max 3 5.8 4.2 Unit MHz V V V
Table 18. Card drivers VDD = 3.3 V; VDD(INTF) = 1.5 V; fCLKIN = 10 MHz; GND = 0 V; Tamb = 25 C; unless otherwise specified. Symbol Vo(inact) Io(inact) VCC Parameter inactive mode output voltage inactive mode output current supply voltage Conditions
[1]
Min 0 0 [2]
Typ -
Max 0.1 0.3 -1
Unit V V mA
Supply voltage for the card: pin VCC
no load Io(inact) = 1 mA at grounded pin VCC Active mode; 2.7 V < VDD < 6.5 V 5 V card; ICC < 60 mA; VCC = 5 V 3 V card; ICC < 55 mA; VCC = 3 V 1.8 V card; ICC < 30 mA; VCC = 1.8 V Active mode; AC current pulses with I < 200 mA, t < 400 ns and f < 20 MHz 5 V card; current pulses of 40 nAs 3 V card; current pulses of 24 nAs 1.8 V card; current pulses of 15 nAs
[2]
4.75 2.80 1.65
5 3 1.8
5.25 3.15 1.95
V V V
4.65 2.76 1.62 -
-
5.35 3.24 1.98 350
V V V mV
Vripple(p-p) ICC
peak-to-peak ripple voltage supply current
on VCC; 20 kHz < f < 200 MHz VDD > 2.7 V 5 V card; VCC = 0 V to 5 V 3 V card; VCC = 0 V to 3 V 1.8 V card; VCC = 0 V to 1.8 V VCC shorted to GND 5 V card or 3 V card 1.8 V card
-
-90 -70
-55 -55 -35 -120 -90
mA mA mA mA mA
SR
slew rate
rise or fall; maximum load capacitor CL = 300 nF 5 V card 3 V card 1.8 V card 0.080 0.050 0.025 0.140 0.200 0.080 0.110 0.045 0.080 V/s V/s V/s
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Table 18. Card drivers ...continued VDD = 3.3 V; VDD(INTF) = 1.5 V; fCLKIN = 10 MHz; GND = 0 V; Tamb = 25 C; unless otherwise specified. Symbol Vo(inact) Io(inact) VOL VOH tr tf Vo(inact) Io(inact) VOL VOH tr tf fCLK SR Vo(inact) Io(inact) VOL VOH Parameter inactive mode output voltage inactive mode output current LOW-level output voltage HIGH-level output voltage rise time fall time inactive mode output voltage inactive mode output current LOW-level output voltage HIGH-level output voltage rise time fall time frequency on pin CLK clock duty cycle slew rate inactive mode output voltage inactive mode output current LOW-level output voltage HIGH-level output voltage Conditions no load Io(inact) = 1 mA at grounded pin RST IOL = 200 A IOH < -200 A CL = 30 pF CL = 30 pF no load Io(inact) = 1 mA at grounded pin CLK IOL = 200 A IOH < -200 A CL = 30 pF CL = 30 pF operational CL = 30 pF rise and fall; CL = 30 pF no load Io(inact) = 1 mA at grounded pin I/O IOL = 1 mA no DC load IOH < -20 A IOH < -40 A VIL VIH IIL LOW-level input voltage HIGH-level input voltage LOW-level input current at pin I/O; VIL = 0 V VCC = 5 V VCC = 3 V ILIH HIGH-level input leakage current at pin I/O; VIH = VCC
[3] [3] [3]
Min 0 0 0 0
Typ -
Max 0.1 0.3 -1 0.3 VCC 0.1 0.1 0.1 0.3 -1 0.3 VCC 8 8 10 55 0.1 0.3 -1 0.3
Unit V V mA V V s s V V mA V V ns ns MHz % V/ns V V mA V
Reset output to the card: pin RST
VCC - 0.5 0 0 0 0 -
Clock output to the card: pin CLK
VCC - 0.5 0 45 0.2 0 0 0.9VCC 0.8VCC 0.75VCC -0.3 1.5 -
Data lines: pins I/O, C4 and C8
VCC + 0.1 V VCC + 0.1 V VCC + 0.1 V +0.8 VCC 600 500 10 V V A A A
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Table 18. Card drivers ...continued VDD = 3.3 V; VDD(INTF) = 1.5 V; fCLKIN = 10 MHz; GND = 0 V; Tamb = 25 C; unless otherwise specified. Symbol Ipu td Parameter pull-up current delay time Conditions at pin I/O; VOH = 0.9VCC; CL = 30 pF between edges on pin I/O and pin I/OUC; corresponds to width of active pull-up pulse inputs; from VIL(max) to VIH(min) output transition time; from 10 % of VCC to 90 % of VCC; CL < 30 pF; no DC load on pin I/O between pin I/O and VCC on pin I/O
[3] [3] [3] [3][4]
Min -1 -
Typ 500
Max 650
Unit mA ns
tr tTLH Ci Rpu(int) fmax
rise time clock rise time input capacitance internal pull-up resistance maximum input clock frequency LOW-level input voltage HIGH-level input voltage
10 -
13.5 -
1.5 0.1 10 17 500
s s pF k kHz
[3]
Card presence input: pin PRES, active-HIGH when pin SPRES = LOW or active-LOW when pin SPRES = HIGH VIL VIH ILIL ILIH 0.7VDD 0 10 -40 -5 0.3VDD 5 40 -10 0 V V A A A A
LOW-level input leakage VI = 0.3VDD; pin SPRES = HIGH current VI = 0.3VDD; pin SPRES = LOW HIGH-level input leakage current VI = 0.7VDD; pin SPRES = HIGH VI = 0.7VDD; pin SPRES = LOW
[1] [2] [3] [4]
Two ceramic multilayer capacitors of minimum 100 nF with low Equivalent Series Resistance (ESR) should be used in order to meet these specifications. Output voltage towards the card, including ripple. Pin I/O has an internal 15 k pull-up resistor to VCC. Pin I/OUC has an internal 11 k pull-up resistor to VDD(INTF).
Table 19. Sequencer and clock counter VDD = 3.3 V; VDD(INTF) = 1.5 V; fCLKIN = 10 MHz; GND = 0 V; Tamb = 25 C; unless otherwise specified. Symbol tact tdeact Parameter activation time deactivation time Conditions total sequence total sequence Min 60 Typ 80 Max 135 100 Unit s s
Table 20. Interface signals to host controller VDD = 3.3 V; VDD(INTF) = 1.5 V; fCLKIN = 10 MHz; GND = 0 V; Tamb = 25 C; unless otherwise specified. Symbol VOL VOH VIL VIH IIL ILIH
TDA8023_1
Parameter I/OUC[1] LOW-level output voltage HIGH-level output voltage LOW-level input voltage HIGH-level input voltage LOW-level input current HIGH-level input leakage current
Conditions IOL = 1 mA no DC load IOH < -10 A
Min 0 0.9VDD(INTF) -0.3 0.7VDD(INTF)
Typ -
Max 0.3 VDD(INTF) + 0.2 VDD(INTF) + 0.2 0.25VDD(INTF) VDD(INTF) + 0.3 600 10
Unit V V V V V A A
Data line: pin
0.75VDD(INTF) -
VIL = 0 V VIH = VDD(INTF)
-
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Table 20. Interface signals to host controller ...continued VDD = 3.3 V; VDD(INTF) = 1.5 V; fCLKIN = 10 MHz; GND = 0 V; Tamb = 25 C; unless otherwise specified. Symbol tr tTLH Parameter rise time clock rise time Conditions input; from VIL(max) to VIH(min) output transition time; from 10 % to 90 % of VDD(INTF); CL < 30 pF between pin I/OUC and pin VDDI
[1]
Min -
Typ -
Max 1 0.1
Unit s s
Rpu(int)
internal pull-up resistance
11
15
19
k
Clock input: pin CLKIN fCLKIN VIL VIH tr tf VIL VIH ILIL ILIH Ci VOL ILH VIL VIH VOL1 ILH ILL frequency on pin CLKIN LOW-level input voltage HIGH-level input voltage rise time fall time LOW-level input voltage HIGH-level input voltage LOW-level input leakage current HIGH-level input leakage current input capacitance LOW-level output voltage HIGH-level leakage current LOW-level input voltage HIGH-level input voltage LOW-level output voltage HIGH-level leakage current LOW-level leakage current IOL = 3 mA input or output depends on the pull-up resistance; input or output Io = 2 mA VDD(INTF) > 2 V 1.5 V < VDD(INTF) < 2 V VDD(INTF) > 2 V 1.5 V < VDD(INTF) < 2 V 0 0 0 0.7VDD(INTF) -0.3 0.7VDD -0.3 0.7VDD 25 0.3VDD(INTF) 0.15VDD(INTF) VDD(INTF) + 0.3 VDD(INTF) + 0.3 0.1 / fCLKIN 0.1 / fCLKIN 0.3VDD(INTF) VDD(INTF) + 0.3 1 1 10 0.3 10 0.3VDD 6.5 0.3 1 1 MHz V V V ns ns ns V V A A pF V A V V V A A
0.85VDD(INTF) -
Logic inputs: pins SAD0, SPRES and SDWN
Interrupt line: pin INT; open-drain active-LOW output
Serial data input/output: pin SDA; open-drain
Serial clock input: pin SCL VIL VIH ILIH IIL LOW-level input voltage HIGH-level input voltage HIGH-level input leakage current LOW-level input current depends on the pull-up resistance -0.3 0.7VDD 0.3VDD 6.5 1 1 V V A A
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Low power IC card interface
Table 20. Interface signals to host controller ...continued VDD = 3.3 V; VDD(INTF) = 1.5 V; fCLKIN = 10 MHz; GND = 0 V; Tamb = 25 C; unless otherwise specified. Symbol I2C-bus fSCL tBUF tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tr tf tSU;STO
[1] [2]
Parameter timing; see Figure 7 SCL clock frequency bus free time between a STOP and START condition hold time (repeated) START condition LOW period of the SCL clock HIGH period of the SCL clock set-up time for a repeated START condition data hold time data set-up time rise time of both SDA and SCL signals fall time of both SDA and SCL signals set-up time for STOP condition
Conditions
Min 0 1.3
Typ -
Max 400 300 300 -
Unit kHz s s s s s ns ns ns ns s
hold time after which first clock pulse is generated
0.6 1.3 0.6 0.6
[2]
0 100 0.6
Pin I/OUC has an internal 11 k pull-up resistor to VDD(INTF). The hold time required (not greater than 300 ns) to bridge the undefined region of the falling edge of SCL must be internally provided by a transmitter.
Table 21. Protection and limitations VDD = 3.3 V; VDD(INTF) = 1.5 V; fCLKIN = 10 MHz; GND = 0 V; Tamb = 25 C; unless otherwise specified. Symbol Tamb Tsd IIlim IOlim Parameter ambient temperature shutdown temperature input current limit output current limit at die on pin I/O on pin I/O on pin CLK shutdown current; on pin RST shutdown current; on pin VCC
[1] Pin I/O has an internal 15 k pull-up resistor to VCC.
[1] [1]
Conditions
Min -40 -15 -15 -70 -20 -
Typ 150 -90
Max +85 +15 +15 +70 +20 -
Unit C C mA mA mA mA mA
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SDA tBUF SCL P S tHD;STA tHIGH tLOW tf S tHD;STA P
tr
tHD;DAT
tSU;DAT
tSU;STA
tSU;STO
mba705
P = STOP condition; S = START condition.
Fig 7. Timing requirements for the I2C-bus
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12. Application information
VDD
R3 10 k C16(1)
IC1 VDD IC2 HOST CONTROLLER VDD GND INT SDA SCL CLKout I/OAUX
4.7 k C20 100 nF
100 nF
VUP INT SDWN VDDI SDA SCL SAD0 SPRES
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22
SAP SBP VDD VDDP SBM
C19(1) C15 100 nF
4.7 k
GNDP 100 nF SAM VDD CDEL PORADJ PRES RST VCC CLK GNDC
P1 10 k C17(1) 100 nF CDEL 22 nF
TDA8023TT
VDD
21 20 19 18 17 16 15
VDD
CLKIN GND I/OUC C8 C4 I/O
C29 100 nF
C13(2) 68 nF
C18(1) 100 nF
CARD READER normally closed C5I C6I C7I C8I C1I C2I C3I C4I K1 K2
Rp 10 k
VDD
001aag341
(1) Low-ESR capacitor, placed near the IC. (2) Low-ESR capacitor, placed near the C1 contact.
Fig 8. Application diagram: typical TDA8023TT application with capacitive DC-to-DC converter
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VDD
R3 10 k C16(1)
IC1 VDD IC2 HOST CONTROLLER VDD GND INT SDA SCL CLKout I/OAUX
4.7 k C20 100 nF
VUP INT SDWN VDDI SDA SCL SAD0 SPRES
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22
SAP SBP VDDP SBM GNDP SAM VDD CDEL PORADJ PRES RST VCC CLK GNDC
D1 BAT54
C8 4.7 F 16 V
100 nF
VDD
L1 6.8 H C15 100 nF
4.7 k
TDA8023TT
CDEL 22 nF
VDD
21 20 19 18 17 16 15
VDD
CLKIN GND I/OUC C8 C4 I/O
P1 10 k
C29 100 nF
C13(2) 68 nF
C18(1) 100 nF
CARD READER normally open C5I C6I C7I C8I C1I C2I C3I C4I K1 K2
VDD
001aag342
(1) Low-ESR capacitor, placed near the IC. (2) Low-ESR capacitor, placed near the C1 contact.
Fig 9. Application diagram: typical TDA8023TT application with inductive DC-to-DC converter
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13. Package outline
TSSOP28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm SOT361-1
D
E
A
X
c y HE vMA
Z
28
15
Q A2 pin 1 index A1 (A 3) A
Lp L detail X
1
e bp
14
wM
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 9.8 9.6 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.8 0.5 8 o 0
o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT361-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19
Fig 10. Package outline SOT361-1 (TSSOP28)
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14. Soldering
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".
14.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
14.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
* Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
* * * * * *
Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus PbSn soldering
14.3 Wave soldering
Key characteristics in wave soldering are:
* Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
* Solder bath specifications, including temperature and impurities
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14.4 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 11) than a PbSn process, thus reducing the process window
* Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 22 and 23
Table 22. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 23. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220
Package thickness (mm)
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 11.
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temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 11. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
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15. Revision history
Table 24. Revision history Release date 20070716 Data sheet status Product data sheet Change notice Supersedes Document ID TDA8023_1
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16. Legal information
16.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
16.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP B.V.
17. Contact information
For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com
TDA8023_1
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 -- 16 July 2007
31 of 32
NXP Semiconductors
TDA8023
Low power IC card interface
18. Contents
1 2 3 4 5 6 7 7.1 7.2 8 8.1 8.2 8.2.1 8.2.2 8.2.3 8.2.4 8.3 8.3.1 8.3.2 8.3.3 8.3.4 8.3.5 8.4 8.4.1 8.4.2 8.5 8.6 8.6.1 8.6.2 8.7 9 10 11 12 13 14 14.1 14.2 14.3 14.4 15 16 16.1 16.2 16.3 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 6 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . 6 Voltage supervisor . . . . . . . . . . . . . . . . . . . . . . 6 Without external divider on pin PORADJ . . . . . 6 With external divider on pin PORADJ. . . . . . . . 7 External capacitor on pin CDEL . . . . . . . . . . . . 7 Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . 8 I2C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . . 8 Bus conditions . . . . . . . . . . . . . . . . . . . . . . . . . 8 Data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Device addressing . . . . . . . . . . . . . . . . . . . . . . 9 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 DC-to-DC converter . . . . . . . . . . . . . . . . . . . . 12 Capacitive configuration . . . . . . . . . . . . . . . . . 12 Inductive configuration . . . . . . . . . . . . . . . . . . 13 VCC buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Sequencer and clock counter . . . . . . . . . . . . . 13 Activation sequence . . . . . . . . . . . . . . . . . . . . 13 Deactivation sequence . . . . . . . . . . . . . . . . . . 15 Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 16 Thermal characteristics. . . . . . . . . . . . . . . . . . 16 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 17 Application information. . . . . . . . . . . . . . . . . . 24 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 26 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Introduction to soldering . . . . . . . . . . . . . . . . . 27 Wave and reflow soldering . . . . . . . . . . . . . . . 27 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 27 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 28 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 30 Legal information. . . . . . . . . . . . . . . . . . . . . . . 31 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 31 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 16.4 17 18 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Contact information . . . . . . . . . . . . . . . . . . . . 31 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 16 July 2007 Document identifier: TDA8023_1

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